Silicon carbide (which will be referred to as SiC) has a wide band gap, and its maximum breakdown electric field is larger than that of silicon (which will be referred to as Si) by one order of magnitude. Thus, SiC has been highly expected to be used as a material for power semiconductor devices in the next generation. Various types of electron devices have been manufactured using a wafer of a single crystal, such as 4H--SiC or 6H--SiC, and, in particular, the use of such a single-crystal wafer has been considered important when applied to high-temperature, power devices. The single crystal as indicated above is formed as alpha-phase SiC in which a zinc-blende structure and a wurtzite structure are superposed on each other. In addition, a beta-phase SiC crystal called 3C--SiC is known. Using the alpha-phase or beta-phase SiC crystal, various types of semiconductor devices, including Shottky diode, vertical MOSFET, and thyristor, which may be used as power devices, and CMOS-IC as a general-purpose semiconductor device, have been fabricated and tested in recent years, and it has been confirmed that these devices exhibit far more excellent characteristics than conventional Si semiconductor devices. (Refer to Weitzel, C. W. et al.: IEEE Trans. on Electron Devices, vol. 43, No. 10, pp. 1732-1741 (1997)).
As one example of known SiC semiconductor devices, the structure of a vertical MOSFET and a method for manufacturing the MOSFET will be explained below.
FIG. 9(a) is a cross-sectional view of a unit cell of a trench type MOSFET. In the structure shown in FIG. 9(a), n source region 13 is formed in a surface layer of p base region 12 laminated on n drift layer 11b, and a trench 14 is formed such that it extends from the surface of the substrate into the n drift layer 11b. Gate electrode layer 16 is formed or embedded within the trench 14 with a gate oxide film 15 interposed between the electrode layer 16 and the inner wall of the trench 14.
With this arrangement, when a voltage is applied to the gate electrode layer 16, channels 20 are induced in surface portions of the p base regions 12 which face the gate electrode layer 16, so that the n source regions 13 and the n drift layer 11b are electrically shortened. As a result, current is allowed to flow from drain electrode 18 formed on the rear surface of n.sup.+ substrate 11a under the n drift layer 11b, to source electrode 17 formed on the surface of the n source regions 13. When the voltage applied to the gate electrode layer 16 is removed, the drain electrode 18 and source electrode 17 are electrically disconnected from each other. Thus, the vertical MOSFET of FIG. 9 performs a switching function with voltage applied to or removed from the gate electrode layer 16.
FIG. 10(a) through FIG. 10(e) and FIG. 11(a) through FIG. 11(c) are cross-sectional views showing the flow of the process of fabricating the structure as described above. The process shown in these figures is only a part of the whole process of producing the semiconductor device, in particular, a process of forming junctions which is associated with the present invention.
Initially, n drift layer 11b having high resistance and p base layer 12 are epitaxially grown on n.sup.+ substrate 11a, as shown in FIG. 10(a). Then, a polycrystalline silicon (polysilicon) layer 1 is deposited on the p base layer 12 by reduced-pressure CVD, and patterned by photolithography, to provide a mask. Using the mask thus formed, n-type impurities, such as phosphorous ions 13a, are implanted into the p base layer 12, as shown in FIG. 10(b). In this figure, reference numeral 13b denotes phosphorous atoms implanted in this manner.
After removing the mask, heat treatment is conducted to activate the implanted impurities, thereby to form n source region 13, as shown in FIG. 10(c).
Aluminum film 2 that provides an etching mask material is applied by sputtering to the surfaces of the p base layer 12 and n source region 13, and patterned by photolithography. By using the patterned aluminum film 2 as a mask, trench 14 is formed by plasma etching using carbon tetrafluoride (CF.sub.4) and oxygen, to a depth that reaches the inside of the n drift layer 11b.
Gate insulating film 15 which consists of a silicon dioxide film (hereinafter referred to as SiO.sub.2 film) is formed by thermal oxidation on the inner wall of the trench 14 and the surface of the SiC substrate, as shown in FIG. 11(a). Thereafter, a polycrystalline silicon layer is deposited in the trench 14 and patterned by photolithography, thereby to provide gate electrode layer 16, as shown in FIG. 11(b).
Subsequently, phosphorous glass is deposited by reduced-pressure CVD to provide an interlayer insulating film 19, and openings or windows are formed through the insulating film 19, so that source electrodes 17 are formed in contact with the n source regions 13. Although not illustrated in FIG. 11(c), drain electrode is formed on the rear surface of the n.sup.+ substrate 11a.
The use of the SiC substrate suffers from two problems, namely, (1) impurities that are introduced into the SiC substrate by ion implantation are less likely to be activated, and (2) the impurities introduced by ion implantation hardly diffuses in the SiC substrate, though these problems do not arise when a silicon substrate is employed. Accordingly, it is easier to produce the trench type MOSFET that can be formed by epitaxial growth, rather than diffusion of impurities.
The above-described trench structure is also advantageously employed by Si devices. This is because the channel regions 20 are formed in the vertical direction in this structure, and therefore cells each performing a switching function can be closely positioned with high density, which leads to an improved area efficiency of the substrate, and improved characteristics of the device due to its geometry.
Recently, Shenoy, J. N. and others reported fabrication of a planar type MOSFET having a high breakdown voltage (as disclosed in IEEE Electron Device Lett., 18(3), 93(1997). FIG. 9(b) is a cross-sectional view showing a unit cell of the MOSFET.
In FIG. 9(b), p base regions 22 are formed in a surface layer of n drift layer 21b that is laminated on n.sup.+ substrate 21a, and n source regions 23 are formed in surface layers of the p base regions 22. Gate electrode layer 26 is formed on gate insulating film 25 which is formed on the surface of exposed portions of the p base regions 22 and n drift layer 21b that are interposed between two n source regions 23. Source electrode 27 is formed on the n source regions 23, and drain electrode 28 is formed on the rear surface of the n.sup.+ substrate 21a.
In this case, too, when a voltage is applied to the gate electrode layer 26, channels 30 are induced in surface portions of the p base regions 22 located right under the gate electrode layer 26, so that current is allowed to flow from the drain electrode 28 to the source electrode 27. When the voltage applied to the gate electrode layer 26 is removed, the drain electrode 28 and the source electrode 27 are electrically disconnected from each other. Thus, the cell of the vertical MOSFET of FIG. 9(b) performs a switching function with voltage applied to or removed from the gate electrode layer 26.
FIG. 12(a) through FIG. 12(g) are cross-sectional views showing the flow of the process of fabricating the structure of FIG. 9(b) as described above. The process shown in these figures is only a part of the whole process of producing the semiconductor device, in particular, a process of forming junctions which is associated with the present invention.
Initially, polycrystalline silicon film 1 as a mask material is formed on a high-resistance drift layer 21b that is formed by epitaxial growth on the surface of n.sup.+ substrate 21a, and then patterned by photography into a desired shape, as shown in FIG. 12(a).
Subsequently, boron ions 22a are implanted at 650.degree. C., as shown in FIG. 12(b). In this step, the acceleration voltage is set to the maximum level of 360 keV, so as to enable multilayer ion implantation. In FIG. 12(b), reference numeral 22b denotes implanted boron atoms.
After removing the polycrystalline silicon film 1, a second mask is formed from a Cr--Au film 3, and nitrogen ions 23a as n-type impurities are implanted using the second mask, as shown in FIG. 12(c). Reference numeral 23b denotes nitrogen ions thus implanted. The impurity atoms implanted in this manner are activated by carrying out heat treatment at 1600.degree. C. for 30 min., so as to form p base regions 22 and n source regions 23, as shown in FIG. 12(d).
In the next step of FIG. 12(e), a silicon dioxide film hereinafter referred to as SiO.sub.2 film) having a thickness of 48 nm is formed by thermal oxidation, to provide gate insulating film 25. A polycrystalline silicon film is then deposited on the gate insulating film 25, and patterned by photolithography into a desired shape, to thus provide gate electrode layer 26, as shown in FIG. 12(f).
Subsequently, phosphorous glass is deposited by reduced-pressure CVD to provide interlayer insulating film 29, and windows are formed through the insulating film 29, so that source electrodes 27 are formed in contact with the n source regions 23. Although not illustrated in FIG. 12, drain electrode is formed on the rear surface of the n.sup.+ substrate 21a.
When forming the p base regions 22 and n source regions 23 according to the above-described method, impurities are implanted to a relatively large depth, by increasing the acceleration voltage during ion implantation, so as to solve the problem of diffusion of the impurities as described above.
The trench-type MOSFET as shown in FIG. 9(a) suffers from a structural problem that an electric field is concentrated at corner portions of the trench. Since SiC used as a semiconductor material, in particular, has a far larger electric field strength than silicon, a relatively large electric field is applied to the corner portions of the gate insulating film 15 formed in the trench. This may result in a fatal problem that dielectric breakdown of the oxide film takes place at the corner portions, and normal breakdown voltage characteristics cannot be obtained.
The boundary condition of the electric field strength at the interface between the semiconductor and the gate insulating film upon application of voltage is represented by: EQU .epsilon.iEi=.epsilon.sEs (1)
where .epsilon.i, .epsilon.s are dielectric constants of the gate insulating film and semiconductor, respectively, and Ei, Es are electric field strengths of the gate insulating film and semiconductor, respectively. From the boundary condition as indicated above, the electric field of the gate insulating film is represented by the following equation. ##EQU1## Since .epsilon.s of Si is 11.7 and .epsilon.i of the SiO.sub.2 film is 3.8, an electric field which is about 3 times as much as that of Si substrate is applied to the gate insulating film where a breakdown electric field is applied to the Si substrate. On the other hand, .epsilon.s of SiC is 10.2, which is not so different from that of Si, but its breakdown electric field is larger than that of Si by about one order of magnitude, as mentioned above. In the SiC device, therefore, an electric field that is ten times as high as that in the case of the Si device is applied to the gate insulating film.
Furthermore, the trench structure as shown in FIG. 9(a) includes corner portions. Since the electric field is concentrated at the corner portions, the SiC device cannot take advantage of its inherent characteristic of high breakdown electric field. Namely, as the voltage applied to the device is increased, the gate insulating film reaches its breakdown electric field before the semiconductor reaches its breakdown electric field, thus causing the device to break down.
In the planar type MOSFET as shown in FIG. 9(b), on the other hand, no corner portion is present, unlike the trench-type MOSFET, and therefore excessive concentration of an electric field does not take place. Thus, the planar type MOSFET is free from the problem of the breakdown voltage of the oxide film as encountered in the trench structure.
In the planar type MOSFET, however, ions, in particular, p type ions, need to be implanted at 600.degree. C. or higher, and heat treatment at 1500.degree. C. or higher is required for activating the ions thus implanted. While SiO.sub.2 film is normally used as a gate insulating film, and polycrystalline silicon is used for forming a gate electrode, the SiO.sub.2 film softens at 1300.degree. C. or higher, and polycrystalline silicon has a fusing point of 1412.degree. C. Where the SiO.sub.2 film and polycrystalline silicon are used to provide the gate insulating film and gate electrode layer, therefore, heat treatment cannot be conducted at such a high temperature as indicated above after these film and layer are formed. Also, a mask used for ion implantation must be made of a heat resisting material, and therefore the process of forming a wafer is tremendously limited or restricted.
In order to form deep junctions through ion implantation, the acceleration voltage needs to be increased. However, the depth of the junctions formed by ion implantation can be only 0.5 .mu.m even if the ions are implanted with the acceleration voltage of 300 keV. It is thus difficult to realize pn junctions having a sufficiently large depth even if the acceleration voltage is increased. In addition, radioactive rays may radiate during a high-energy ion implantation, and an expensive implantation apparatus may be needed to perform the high-energy ion implantation.